1. Technical Field
The present invention relates generally to data processing and, in particular, to handling updates to partial cache lines in a data processing system.
2. Description of the Related Art
A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of processor-addressable memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.
Cache memories are commonly utilized to temporarily buffer cache lines that might be accessed by a processor in order to speed up processing by reducing access latency introduced by having to load needed data and instructions from memory. In some multiprocessor (MP) systems, the cache hierarchy includes at least two levels. The level one (L1), or upper-level cache is usually a private cache associated with a particular processor core and cannot be directly accessed by other cores in an MP system. Typically, in response to a memory access instruction such as a load or store instruction, the processor core first accesses the directory of the upper-level cache. If the requested cache line is not found in the upper-level cache, the processor core then accesses one or more lower-level caches (e.g., level two (L2) or level three (L3) caches) for the requested cache line.
With some workloads, updates are performed to scattered locations in memory. To perform each such update, a conventional cache hierarchy retrieves a full cache line of data from system memory and populates one or more levels of cache with the cache line. It is recognized herein that it is wasteful and inefficient to retrieve the entire cache line when an update will only be made to a small portion of the cache. In addition, placing the line in the cache is also wasteful since that line is unlikely to be accessed again in the near future in such workloads.